有酬cpld设计开发

By: fpganewbie

<p>我在仿真的时候，说有无输出的错误，可是仿真程序本身就是不要输出的，请教这是怎么一回事呢？</p><p>`timescale 1ns/1ns</p><p>`include "count4_1.v"</p><p>module coun4_1_tp;<br/>reg clk,reset;&nbsp;<br/>wire[3:0] out;&nbsp;<br/>parameter dely=100;</p><p><br/>count4_1 mycount(out,reset,clk);<br/>always #(dely/2) clk = ~clk;&nbsp;</p><p>initial</p><p>begin&nbsp;</p><p>clk =0; reset=0;</p><p>#dely&nbsp;reset=1;</p><p>#dely&nbsp;reset=0;</p><p>#(dely*20) $finish;</p><p>end</p><p>initial $monitor($time,,,"clk=%d reset=%d out=%d", clk, reset,out);</p><p>endmodule</p><p></p><p><strong><font color="#ff0000">error：project has no output or bidirection&nbsp;pins in the top_level design file</font></strong></p><p></p><p>这是怎么一回事呢？怎么解决呢？</p><p></p>
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