我编的一段verilog hdl程序,有点问题请教大家

By: lizarduke

小弟初学veriloghdl，编了个程序，是用于ccd驱动的，编译时0个错误，但有13个warning，仿真出来的波形也不是我所想要的，编译时说 初始化语句块initial无效 ，不知何故，望高手指点，不胜感激！！！以下是源程序
siki}m
a rac%bxmodule ccddrive (clk,sh,t1,t2,rs,cp);
  input clk;  //10mhz
  output sh,t1,t2,rs,cp;

  reg[11:0] countsh;  //3820 12h'eec
}fn6it&y9r  reg[3:0] countt;   //5
  reg[4:0] countrs;  //8
?"d/qc9m?`"`1?i])n?  reg[4:0] countcp;  //8
  reg[4:0] countend;  //8
-d&@)y?ns
omw(i,la*m:i(q  reg reg_sh,reg_t1,reg_t2,reg_rs;
  
z&ijp.xhinitial
   begin
      countsh=0;
5o4dsm'h7{      countt=0;
      countrs=0;
      countcp=0;
hd?e!k7i pog#r6z      countend=0;
f'c*pomdkop      reg_sh=0;
*p#z#m][hw8|      reg_t1=1;
b wuc2ql
p      reg_t2=0;
9u @:\)tx#e|:co      reg_rs=1;
   end
5j}p@q"uk
  always @ (posedge clk)
!`"f$ts;fhf    begin
!f+g)c3_j)u0crd#f1r       countsh=countsh+1;     //sh计数
       countt=countt+1;       //t1,t2计数
       countrs=countrs+1;     //rs计数
       countcp=countcp+1;     //cp计数
     if(countsh==3805) reg_sh=1;  //sh置高电平
     if(countsh==3820)
3[5}p;?/om.|v/o       begin
        reg_sh=0;  //sh置低电平
        countsh=0;   //sh计数清零
       end
     if(countt==5)   //500ns
&~!xo2m4i@       begin
;khk9o&ppc'g        if(countsh>=3805&&countsh<3820)
+w3hb4c_$g^ak
o          begin
s&],fq_annp            reg_t1=1;
            reg_t2=0;
u!uj}_n!am          end
         else
          begin
            reg_t1=~reg_t1;
q:a6ra.}y@"b+m:\ |%[            reg_t2=~reg_t1;
b+y(wf]6]#k!ce(a"~            countt=0;
          end
       end
   
     if(countrs==countend)
       begin
u/a!xu.mwl[         reg_rs=~reg_rs;
         countrs=0;
         if(reg_rs)  countend=2;
         else  countend=8;
       end
9t:i8t3un5i.w  end
7h:gukuau5~assign sh=reg_sh,t1=reg_t1,t2=reg_t2,rs=reg_rs;
endmodule
)t`4m2~b x6| h}k


编译时的warning
}#i}5x?
warning (10101): verilog hdl unsupported feature warning at ccddrive.v(14): initial construct is not supported and will be ignored

@7r!i-cfwarning (10230): verilog hdl assignment warning at ccddrive.v(28): truncated value with size 32 to match size of target (12)

%y8\0n q"q"awarning (10230): verilog hdl assignment warning at ccddrive.v(29): truncated value with size 32 to match size of target (4)

warning (10230): verilog hdl assignment warning at ccddrive.v(30): truncated value with size 32 to match size of target (5)
zh"nz-b&u:b
)x3s-mlnyu:_'swarning (10230): verilog hdl assignment warning at ccddrive.v(31): truncated value with size 32 to match size of target (5)
a]%nkpwy
-a5j_%e_warning (10034): output port "cp" at ccddrive.v(3) has no driver
/l|'iff4p.z
nf/e}um*[6uxm*ilwarning: reduced register "countend[0]" with stuck data_in port to stuck value gnd
)?0r+w/siy~!w
warning: reduced register "countend[2]" with stuck data_in port to stuck value gnd

warning: reduced register "countend[4]" with stuck data_in port to stuck value gnd
j*t:~(wz

zgm~`awarning: output pins are stuck at vcc or gnd

!jg/i4v7i        warning: pin "cp" stuck at gnd
5fl;gaa2z%o!n|9o\|*\
@0j[r4t`gc,xf7swarning: timing analysis does not support the analysis of latches as synchronous elements for the currently selected device family

\-}wp)rpjwarning: found pins functioning as undefined clocks and/or memory enables
r&t/h5kgo0do6\        info: assuming node "clk" is an undefined clock
该篇文章发表于:设计互动 (www.ccflash.org),复制请保留此行.

Username