请帮我看一个串入并出移位寄存器程序

By: 扁舟

<p>library ieee;<br/>use ieee.std_logic_1164.all;<br/>entity y is<br/>&nbsp; port(d,clk:in std_logic;<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; q:out std_logic_vector (3 downto 0);<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; h:out std_logic_vector (3 downto 0));<br/>end y;<br/>architecture hav of y is<br/>&nbsp;&nbsp;&nbsp; signal h1:std_logic_vector (3 downto 0);<br/>&nbsp;&nbsp;&nbsp; signal q1:std_logic_vector (3 downto 0);<br/>&nbsp;&nbsp;&nbsp; signal e:std_logic;<br/>begin<br/>&nbsp; process(clk)<br/>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; variable c:integer range 0 to 8;<br/>&nbsp; begin<br/>&nbsp;&nbsp;&nbsp;&nbsp; c:=0;<br/>&nbsp;&nbsp;&nbsp; if(clk'event and clk='1') then<br/>&nbsp;&nbsp;&nbsp;&nbsp; h1(0)&lt;=h1(1);<br/>&nbsp;&nbsp;&nbsp;&nbsp; h1(1)&lt;=h1(2);<br/>&nbsp;&nbsp;&nbsp;&nbsp; h1(2)&lt;=h1(3);<br/>&nbsp;&nbsp;&nbsp;&nbsp; h1(3)&lt;=q1(0);<br/>&nbsp;&nbsp;&nbsp;&nbsp; q1(0)&lt;=q1(1);<br/>&nbsp;&nbsp;&nbsp;&nbsp; q1(1)&lt;=q1(2);<br/>&nbsp;&nbsp;&nbsp;&nbsp; q1(2)&lt;=q1(3);<br/>&nbsp;&nbsp;&nbsp;&nbsp; q1(3)&lt;=d;<br/>&nbsp;&nbsp;&nbsp;&nbsp; c:=c+1;<br/>&nbsp;&nbsp; if(c=8) then<br/>&nbsp;&nbsp; e&lt;='1';<br/>&nbsp;&nbsp; c:=0;<br/>else<br/>&nbsp;e&lt;='0';<br/>end if;<br/>if(e='1') then<br/>&nbsp;h(0)&lt;=h1(0);<br/>&nbsp;h(1)&lt;=h1(1);<br/>&nbsp;h(2)&lt;=h1(2);<br/>&nbsp;h(3)&lt;=h1(3);<br/>&nbsp;q(0)&lt;=q1(0);<br/>&nbsp;q(1)&lt;=q1(1);<br/>&nbsp;q(2)&lt;=q1(2);<br/>&nbsp;q(3)&lt;=q1(3);<br/>end if;<br/>end if;<br/>end process;<br/>end hav;<br/></p>
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